SEP 3, 2026 · PREPRINT
LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural Networks
arXiv
This is an unrefereed arXiv preprint describing a novel computational method for circuit design optimization with reported benchmark improvements; it has not undergone peer review.
Reported
Average power reduction6.89%
Timing delay improvement27.48%
DRC violation reduction (post-pla…99.59%