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Life sciences · Preprint
arXiv · September 3, 2026
Raises a question worth testing. It does not answer one.
Para-Pipe is a hierarchical framework for mapping machine learning computational graphs onto heterogeneous System-on-Chips, designed to balance throughput and latency by combining intra- and inter-stage operator parallelism. The work reports engineering optimization results on two specific SoC platforms showing energy efficiency gains, but is a systems computer science preprint without peer review and without direct clinical relevance.
Preprint. Intervention: Para-Pipe hierarchical mapping framework integrating intra- and inter-stage operator parallelism within pipelined architecture on heterogeneous SoCs. Compared with: Purely pipelined strategies and non-pipelined parallel execution on Amlogic and Black Sesame Technology SoCs.
Throughput-optimized Para-Pipe configurations on Amlogic SoC achieved 11.0% average energy efficiency improvement over purely pipelined strategies Para-Pipe showed 23.3% energy efficiency improvement relative to non-pipelined parallel execution on Amlogic SoC Framework generates multiple Pareto-optimal configurations balancing throughput and latency on Amlogic SoC (ARM big.LITTLE CPUs and GPU) and Black Sesame Technology SoC (deep learning accelerator and two DSPs)
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The source did not state who this applies to in practice.
This is a systems computer science paper presenting a novel optimization framework for edge ML inference, not a clinical or biomedical study; it reports engineering design and performance benchmarking on hardware without peer review.
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As edge-based deep learning applications become more complex, optimizing performance on heterogeneous System-on-Chips (SoCs) presents unique challenges. Traditional pipelining techniques distributing the computation across different on-chip processing units, while effective for throughput, do not address the latency demands posed by modern neural networks with complex interdependencies and extensive operator parallelism. There is a potential in leveraging operator parallelism to enable concurrent execution across multiple processing units, thereby reducing inference latency. However, prioritizing pipelining or parallel execution often necessitates a compromise, where optimizing one performance metric adversely impacts the other. This paper introduces Para-Pipe, a hierarchical mapping framework that integrates intra- and inter-stage operator parallelism within a pipelined architecture. Para-Pipe navigates the trade-off between throughput and latency by selectively fine-tuning parallelism levels within and across pipeline stages. This strategy can significantly reduce inter-processor communication overhead, significantly improving energy efficiency. Our evaluation demonstrates that Para-Pipe generates multiple Pareto-optimal configurations, achieving a balance between throughput and latency on an Amlogic SoC equipped with ARM big.LITTLE CPUs and GPU, as well as the Black Sesame Technology SoC featuring a deep learning accelerator and two DSPs. More importantly, throughput-optimized configurations under Para-Pipe on Amlogic SoC show an average energy efficiency improvement of 11.0% over purely pipelined strategies and 23.3% relative to non-pipelined parallel execution.
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